1. Field of the Invention
The present invention relates to a semiconductor device such as a power amplifying transistor and a method of fabricating the same.
2. Description of the Background Art
FIG. 12 is a sectional view showing the structure of a conventional NPN semiconductor device. As shown in FIG. 12, an N-type epitaxial layer 1 is formed on an N-type semiconductor substrate 8, and a base region (P-type region) 2 is formed on the epitaxial layer 1.
An emitter region (N-type region) 4 is selectively formed on the surface of the base region 2, and this emitter region 4 is connected to an emitter electrode 7e through a metal electrode underlayer 6e for an emitter. Further, a base electrode 7b is formed on a portion, which is provided with no emitter region 4, of the base region 2 through a metal electrode underlayer 6b for a base region.
An oxide film 9 is formed between the emitter electrode 7e and the base electrode 7b, in order to isolate these electrodes from each other.
Further, a collector electrode 7c is formed entirely over the lower surface of the semiconductor substrate 8.
Steps of fabricating this semiconductor device are now described. FIG. 13 shows sectional views for illustrating a method of fabricating the conventional semiconductor device shown in FIG. 12. First, an epitaxial layer 1 is formed on a semiconductor substrate 8, as shown at FIG. 13(a). Then, an oxide film (not shown) is formed on the epitaxial layer 1, and a portion of the oxide film for defining a base region 2 (FIG. 13 shows only this portion) is removed by photolithography. Thereafter boron or the like is implanted into this portion by ion implantation, to define the base region 2 through annealing.
Then, another oxide film 9 is formed on the base region 2 as shown at FIG. 13(b), and a portion of the oxide film 9 for defining an emitter region 4 is removed. Thereafter arsenic, phosphorus or the like is implanted into this portion by ion implantation, to define the emitter region 4 through annealing.
Then, a metal electrode underlayer 6 is formed entirely over the surface of the semiconductor device as shown at FIG. 13(c), and a resist film 10 is applied onto the same. Photolithography is carried out on this resist film 10, to partially remove the same while leaving portions for forming a base electrode 7b and an emitter electrode 7e, thereby exposing the metal electrode underlayer 6.
Thereafter plating is performed through the exposed portions of the metal electrode underlayer 6, serving as energization parts, to form the base electrode 7b and the emitter electrode 7e respectively. The resist film 10 is then removed and thereafter the metal electrode underlayer 6 is also removed through the base electrode 7b and the emitter electrode 7e, serving as masks. Then vacuum deposition is performed entirely over the rear surface of the semiconductor device, to define a collector electrode 7c thereon.
The semiconductor device shown in FIG. 12 can be formed through the aforementioned steps.
FIG. 14 is a package diagram showing a wiring state of a plurality of such semiconductor devices, which are connected in series with each other through a common emitter. As shown in FIG. 14, a plurality of (in this figure, three) chip bonding patterns 22 are formed on a dielectric member 21, and semiconductor chips 23, each having the structure shown in FIG. 12, are carried out on the respective chip bonding patterns 22.
Collector electrodes provided on the rear surfaces of the semiconductor chips 23 are connected to the chip bonding patterns 2 through solder members. Further, emitter electrodes 24e to 26e of the semiconductor chips 23 are connected through wires to a grounding pattern 31, which in turn is grounded by grounding through holes 31g.
An input part 27 is first connected to a base electrode 24b of the first-stage chip 23, and the chip bonding pattern 22 carrying the first-stage chip 23 thereon is connected to a base electrode 25b of the second-stage chip 23, while the chip bonding pattern 22 carrying the second-stage chip 23 thereon is connected to a base electrode 26b of the third-stage chip 23, and the chip bonding pattern 22 carrying the third-stage chip 23 thereon is connected to an output part 28, respectively through wires.
In the conventional semiconductor device having the aforementioned structure, the base electrode 7b and the emitter electrode 7e are formed on its surface while the collector electrode 7c is formed on its rear surface.
In general, a high-frequency power amplifying transistor is employed in a common emitter manner as described above, while its base and collector serve as an input and an output respectively.
Therefore, when a plurality of such semiconductor devices are connected in series as shown in FIG. 14, it is necessary to solder the collector electrode 7c, which is provided on the rear surface of each semiconductor device, onto a printed board or the like. In this case, it is necessary to connect the emitter electrode 7e to the substrate by a wire in order to ground the same, while it is necessary to connect a collector, serving as an output, to the base electrode 7b of the next-stage transistor from the substrate by a wire.
However, such a structure is complicated and high-frequency characteristics are deteriorated by inductances of the wires.
In order to integrate such devices, further, it is necessary to take a complicated floating collector structure for exposing the collector electrodes on the surface sides. In this case, collector resistance values are increased due to the floating collector structure, to significantly deteriorate high-frequency characteristics.